HDL & Verification
Writing synthesizable RTL and the testbenches that try to break it.
- Verilog
- VHDL
- SystemC
- RTL design
- Testbenches
- Functional sim
- Waveform debug
- Icarus Verilog
- GTKWave
- Vivado
RTL Design · Timing · Computer Architecture
Lucus Kim
I'm a Computer Engineering student at Texas A&M, emphasis on silicon design. My experience includes writing RTL, timing closure, and cache coherency applications. This past summer I built an agentic AI skill that performs static timing analysis, tested on an IBM Z processor.
- School
- Texas A&M · B.S. CE '27
- Next
- M.S. CE (Fast Track) '28
- Most recent
- IBM Z hardware intern
- Based in
- Austin / College Station
// experience
-
May – Aug 2026
Hardware Developer Intern · IBM, Z Logic Processor
Ran static timing analysis on a next-generation Z processor unit and recovered negative slack through latch extraction, retiming, latch cloning and Vt/drive-strength upgrades. Also built Slack Zero, an agentic timing-closure assistant that cut path triage from two weeks to about ten minutes.
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Aug 2025 – May 2026
Undergraduate Research Assistant · Texas A&M
Added embedding-based semantic retrieval to a RocksDB key-value store and used Google's MUVERA algorithm to compress ColBERT multi-vector outputs into fixed-dimension encodings.
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May 2024 – Present
President · Beta Tau Omega
Lead a 50+ member chapter. Built an attendance-tracking system with Python reporting and a companion iOS app that turns fraternity perks into a lootbox game: members earn gems by attending events and spend them to unlock rewards. Also built an interactive family tree that connects current members to alumni.
What I work with
Skills
From writing and simulating RTL to closing timing and modeling the memory hierarchy.
Timing & Physical Design
Finding and fixing slack on real high-frequency processor hardware.
- STA
- Timing closure
- Setup / hold
- Critical paths
- Retiming
- Clock domains
- Clock gating
- Latch-based design
- Vt / drive strength
- DFT / scan
Computer Architecture
Pipelines, predictors and cache hierarchies, plus the simulators I use to measure them.
- Pipelining
- Hazards & forwarding
- Branch prediction
- Out-of-order
- Cache hierarchy
- MESI / MOESI
- ZSim
- ChampSim
- SPEC CPU2006
- PARSEC
Languages & Tools
Software I use to automate flows, parse reports and build models.
- Python
- C++
- C
- Java
- Bash
- Git
- Linux / UNIX
- Make
- NumPy
- LTspice
- Arduino
- Raspberry Pi
Selected work
Projects
Processors, caches, timing tools and a few things built for my chapter. Open a project for code, write-ups and results.
Get in touch
Let's build
something fast.
I'm looking for RTL design, verification and performance-modeling internships and new-grad roles. If you're hiring, or just want to talk caches and timing closure, reach out.
email
maximus.kim@gmail.com